The present invention relates to a clock timing controller for operating a plurality of LSI (large-scale integration) chips.
Recent advances in semiconductor technologies have made possible the implementation of digital circuitry with LSI chips at modest costs. In a high-speed communications system, each LSI chip is so configured that it provides a particular single function and a plurality of LSI chips of different functions are combined to achieve an intended purpose. For example, digital satellite communications systems require highly sophisticated error coding techniques using high-speed, error coding and decoding circuits. These circuits are divided into functional blocks of different functions and implemented by different LSI chips. Since LSI chips are constructed of CMOS circuitry, they are operated in a parallel fashion to compensate for the inherent low-speed capability of the CMOS circuits. Although satisfactory parallel operation can be ensured if all the LSI chips are operated on a common clock source, synchronization slippage would occur between LSI chips if each LSI chip has a frequency divider to divide the frequency of the common clock signal for its own internal circuit.